Mounting structures obtained by mounting semiconductor devices such as IC (integrated circuit) and LSI (large scale integration) chips have been known.
With recent miniaturization of electronic apparatuses, a circuit board in which insulating layers and conductive layers are alternately stacked multiple times in the vertical direction has been demanded as the circuit board described above.
Upper and lower conductive layers are connected to each other through a via conductor having conductivity and embedded in the insulating layer. The via conductor has, for example, a tapered shape in which one of the upper end and the lower end is smaller in width than the other (e.g., refer to Patent Document 1).
However, when such a via conductor having a tapered shape is used, stress is easily concentrated at the end of the via conductor having a smaller width compared with the end of the via conductor having a larger width, which poses a problem in that the via conductor is easily detached from the insulating layer. The detachment of the via conductor results in faulty conduction of the circuit board, which decreases the electrical reliability of the circuit board.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 8-116174